LX10 KORNER




Introduction
Skyguider
Z88
Optical Encoders
Hardware
Schematic
Notes



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DIGITAL SETTING CIRCLES PROJECT

Schematic

Below is the schematic of my fully operational digital settings circles interface, SkyGuider. It interfaces the Z88 computer with the encoders fixed to the telescope. Also there is a 512KByte EPROM chip (IC1 - 27C4001) which holds the Z88 software and databases of objects.

IC1 is a 512KByte EPROM chip, IC2 is an octal buffer (acting as a gate), IC3 is an octal latch (an 8 bit register), ICs 4 and 5 are Hewlett Packard quadature decoder/counter interface chips, IC6 is quad 2 input NAND gates and IC7 is a hex Scmitt trigger inverter.

J1 is the connector to the Z88 via one of its slots, probably slot 2. These slots were intended for RAM and ROM cards only and are accessed by the Z80 processor in the Z88 by memory read/write operations. The Z88 also has an I/O expansion connector on the left hand side. I've decided to use the card slot in preference to the expansion for the following reasons:

  • The interface is simpler - only the /SE and /ROE lines from the Z88 need to be considered
  • The interface has an EPROM chip on it providing the necessary software for the Z88 to run
  • The card slot connector is a much more reliable and secure connection

Address lines A0 through to A13 (16K addressing) are provided directly by the Z80 itself. The Z88's special memory architecture provides the address lines A14 through to A19. This means a total of 1MByte of memory can be accessed via the card slot. However SkyGuide uses A19 to select between memory and the encoder interface (via IC3 and IC4). When A19 is high (1) then EPROM memory is selected and the EPROM devices reacts accordingly. When A19 is low (0) then encoder interface is activated. This arrangement allows only 512KBytes of memory on the EPROM to be made available to the Z88 - which is quite sufficient!.

ICs 6 and 7 provide the main interfacing between the selection of the memory and the encoder interface. The Z88 selects the interface card when the /SE line goes low (0).

ICs 4 and 5 (the decoder chips) monitor and count the signal pulses from the encoders on the telescope on their CH A and CH B inputs (via the Schmitt trigger inverters which clean up the signal from the enocoders). When the appropiate signals are set on their SEL and /OE pins. A clock signal is provided on their CLK pins. This is generated by a 6.552MHZ crystal (it was one I had lying around!) via a NAND (IC6D) and a Schmitt trigger NOT gate (IC7B). The crystal could be any frequency provided it is at least 3.2876 MHZ (the Z88 clock speed) to 14 MHZ. The Z88 clock signal cannot be used here as it is not available on the Z88's connector.

The decoder chip's count register can count upto 65535 before clocking around to 0. The count register increments or decrements depending on the direction of the encoder movement. The register is 16 bits in size and is output in two bytes (high or low) on request.

The crystal frequency I'm using means that the encoder signals are being monitored 1.638 million times per second - none should be missed!

The encoder interface uses address lines A0 to A7 whose signals are stored into IC3 when its CP line goes high (1). These address line settings are held continuously until the next storage of A0 to A7. The outputs of IC3 are connected to both the decoder chips and LEDs. The address lines have the following meanings:

A0: 0 = select the high byte of decoder's count register, 1 = select the low byte
A1: 0 = enable Decoder 1's (IC4) outputs D0-D7, 1 = set outputs to a high impedence state
A2: 0 = enable Decoder 2's (IC5) outputs D0-D7, 1 = set outputs to a high impedence state
A3: 0 = reset the count registers in both decoder chips to zero, 1 = no reset
A4: 0 = turn direction LED 1 off, 1 = turn LED 1 on
A5: 0 = turn direction LED 2 off, 1 = turn LED 2 on
A6: 0 = turn direction LED 3 off, 1 = turn LED 3 on
A7: 0 = turn direction LED 4 off, 1 = turn LED 4 on

Reading a byte from the encoder interface will make IC2 open its gate and allow the outputs of the selected decoder chip to pass through to the computer's data bus.

Software Control

In order to access the count registers from the encoder interface the Z80 needs to carry out a read instruction from a specfic address. Assuming the Z80's logical 16K memory chunk at 0C000h is set to the encoder interface (i.e. the Z88's memory architecture will supply the address lines A14 to A19 to the address bus when a memory access is made between addresses 0C000h to 0FFFFh; A19 will be set to 0 to access the encoder interface) then the Z80 machine code would have the following source:
 

READ_ENC LD A,(ENC_BUFFER) ;Get last settings of the Encoder register IC3
  AND 11110000B ;Keep LED settings and reset decoder chip control lines
  OR 00001100B ;Read in Decoder 1’s counter high byte (/RST=1, /OE2=1, /OE1=0, SEL=0)
  LD L,A  
  LD H,0C0H ;0C0H means select encoder interface
  LD D,(HL) ;Put Decoder 1’s counter high byte into D
  SET 0,L ;Set SEL to high to get the low byte
  LD E,(HL) ;Put Decoder 1’s counter low byte into E
  AND 11110000B ;Reset the control line settings again
  OR 00001010B ;Read in Decoder 2’s counter high byte (/RST=1, /OE2=0, /OE1=0, SEL=0)
  LD L,A  
  LD B,(HL) ;Put Decoder 2’s counter high byte into B
  SET 0,L ;Set SEL to high to get low byte
  LD C,(HL) ;Put Decoder 2’s count low byte into C
  OR 00001111B ;Disable the decoder chips outputs and reset the inhibit logic in each chip
  LD (ENC_BUFFER),A ;Update ENC_BUFFER
  LD L,A  
  LD (HL),A The contents of A are not actually written anywhere! But the address lines are
  RET   ;DE = Decoder 1’s counter, BC = Decoder 2’ counter

Bits 4,5,6 and 7 of L are used to switch on and off the direction LEDs (1=on, 0= off). Writing to the encoder interface, ensuring bits 0,1,2 and 3 are picked up from ENC_BUFFER can switch on and off the LEDs. Setting bit 3 to 0 will reset the counters in the decoder chips.